package regTest

import chisel3._
import chisel3.util._
import utils._


class RegBundle extends Bundle {
    val in = Input(UInt(2.W))
    val en = Input(Bool())
    val regN1 = Output(UInt(2.W))
    val regN2 = Output(UInt(2.W))
    val regI1 = Output(UInt(2.W))
    val regI2 = Output(UInt(2.W))
    val regN3 = Output(UInt(2.W))
    val regN4 = Output(UInt(2.W))

    val vec = Input(Vec(6, Bool()))
    val vec2vecinit = Output(UInt(6.W))
}


class RegTest extends Module {
    val io = IO(new RegBundle)

    val regN1 = RegNextA(reset, io.in)
    val regN2 = RegNextA(reset, io.in, 0.U(2.W))
    val regI1 = RegInitA(reset, io.in, 1.U(2.W))
    val regI2 = RegInitA(reset, 2.U(2.W))
    val regN3 = RegNextWithEnableA(reset, io.en, io.in)
    val regN4 = RegNextWithEnableA(reset, io.en, io.in, 0.U(2.W))
    io.regN1 := regN1
    io.regN2 := regN2
    io.regI1 := regI1
    io.regI2 := Cat(regI2.asBools.reverse)
    regI2 := io.in
    io.regN3 := regN3
    io.regN4 := regN4
    // io.vec2vecinit := VecInit(io.vec.reverse).asUInt
    io.vec2vecinit := VecInit(io.vec.reverse).asUInt
}